Mips Technologies R4000 - Subblock Ordering; Sequential Ordering

Chapter 9
222 MIPS R4000 Microprocessor User's Manual
9.4 Boot-Mode Settings
Table 9-1 lists the processor boot-mode settings. The following rules apply
to the boot-mode settings listed in this table:
• Bit 0 of the stream is presented to the processor when VCCOk
is first asserted.
• Selecting a reserved value results in undefined processor
behavior.
• Bits 65 to 255 are reserved bits.
• Zeros must be scanned in for all reserved bits.
Table 9-1 Boot-Mode Settings
Serial Bit Value Mode Setting
0
BlkOrder: Secondary Cache Mode block read response ordering
0 Sequential ordering
1 Subblock ordering
1
EIBParMode: Specifies nature of System interface check bus
0
Single error correcting, double error detecting (SECDED) error
checking and correcting mode
1 Byte parity
2
EndBIt: Specifies byte ordering
0 Little-endian ordering
1 Big-endian ordering
3
DShMdDis: Dirty shared mode; enables the transition to dirty shared state
on a successful processor update
0 Dirty shared mode enabled
1 Dirty shared mode disabled
4
NoSCMode: Specifies presence of secondary cache
0 Secondary cache present
1 No secondary cache present
5:6
SysPort: System Interface port width, bit 6 most significant
0 64 bits
1-3 Reserved
7
SC64BitMd: Secondary cache interface port width
0 128 bits
1 Reserved
8
EISpltMd: Specifies secondary cache organization
0 Secondary cache unified
1 Secondary cache split