Mips Technologies R4000 - Maintaining Coherency on Loads and Stores

MIPS R4000 Microprocessor User's Manual 269
Cache Organization, Operation, and Coherency
If either IvdAck* or IvdErr* is asserted before, but not asserted during or
after the first cycle that the external agent asserts ExtRqst*, the processor
restarts before beginning the external request.
External requests must be completed before a processor invalidate or
update completes. They can be completed, provided the processor
receives an asserted ExtRqst* by the external agent either before or during
the same cycle IvdAck* or IvdErr* is asserted.
11.9 Maintaining Coherency on Loads and Stores
Cache coherency protocols maintain data consistency throughout a
multiprocessor environment. Table 11-6 lists the coherency effects of load
and store operations on primary and secondary cache states in a
multiprocessor environment (using an R4000MC processor).
Table 11-6 R4000MC Data Cache Coherency States
† The dirty exclusive primary state allows the primary cache to be written without a
secondary access.
Primary
Cache States
Secondary
Cache States
Action on
Load
Action on
Store
Invalid Any Miss Miss
Shared
Shared
Dirty Shared
None
Read secondary tag. If the coherency
algorithm is Update on Write, then
send update and set the secondary
cache state to Dirty Shared. If the
coherency algorithm is Invalidate on
Write, then send invalidate and set the
primary and secondary cache states to
Dirty Exclusive.
Dirty Exclusive None
Set the primary cache state to Dirty
Exclusive.
Clean Exclusive
Clean
Exclusive
None
Set the primary and secondary cache
states to Dirty Exclusive.
Dirty Exclusive None
Set the primary data cache state to
Dirty Exclusive.
Dirty Exclusive
†
Dirty Exclusive None None