Chapter 12
296 MIPS R4000 Microprocessor User's Manual
Address and Data Cycles
Cycles in which the SysAD bus contains a valid address are called address
cycles. Cycles in which the SysAD bus contains valid data are called data
cycles. Validity is determined by the state of the ValidIn* and ValidOut*
signals (described in Interface Buses, in this chapter).
The SysCmd bus identifies the contents of the SysAD bus during any
cycle in which it is valid. The most significant bit of the SysCmd bus is
always used to indicate whether the current cycle is an address cycle or a
data cycle.
• During address cycles [SysCmd(8) = 0], the remainder of the
SysCmd bus, SysCmd(7:0), contains a System interface command
(the encoding of System interface commands is detailed in
System Interface Commands and Data Identifiers, in this
chapter).
• During data cycles [SysCmd(8) = 1], the remainder of the
SysCmd bus, SysCmd(7:0), contains a data identifier (the
encoding of data identifiers is detailed in System Interface
Commands and Data Identifiers, in this chapter).
Issue Cycles
There are two types of processor issue cycles:
• processor read, invalidate, and update request issue cycles
• processor write request issue cycles.
The processor samples the signal RdRdy* to determine the issue cycle for
a processor read, invalidate, or update request; the processor samples the
signal WrRdy* to determine the issue cycle of a processor write request.
As shown in Figure 12-2, RdRdy* must be asserted two cycles prior to the
address cycle of the processor read/invalidate/update request to define
the address cycle as the issue cycle.
Figure 12-2 State of RdRdy* Signal for Read, Invalidate, or Update Requests
SCycle
1 2 3 4 5 6
SClock
SysAD Bus
Addr
RdRdy*
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