MIPS R4000 Microprocessor User's Manual 297
System Interface
As shown in Figure 12-3, WrRdy* must be asserted two cycles prior to the
first address cycle of the processor write request to define the address
cycle as the issue cycle.
Figure 12-3 State of WrRdy* Signal for Write Requests
The processor repeats the address cycle for the request until the conditions
for a valid issue cycle are met. After the issue cycle, if the processor
request requires data to be sent, the data transmission begins. There is
only one issue cycle for any processor request.
The processor accepts external requests, even while attempting to issue a
processor request, by releasing the System interface to slave state in
response to an assertion of ExtRqst* by the external agent.
Note that the rules governing the issue cycle of a processor request are
strictly applied to determine the action the processor takes. The processor
either:
• completes the issuance of the processor request in its entirety
before the external request is accepted, or
• releases the System interface to slave state without completing
the issuance of the processor request.
In the latter case, the processor issues the processor request (provided the
processor request is still necessary) after the external request is complete.
The rules governing an issue cycle again apply to the processor request.
SCycle
1 2 3 4 5 6
SClock
SysAD Bus
Addr
WrRdy*
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