MIPS R4000 Microprocessor User's Manual 435
Error Checking and Correcting
Fault Detection
Fault detection of an output miscomparison occurs at the end of the bus
cycle (the length of the cycle is programmed at boot-mode time; see
Chapter 9). When the R4400 processor is in master state, outputs at the
System interface are checked at the end of every System interface cycle. At
the Secondary Cache interface, outputs are checked at the end of each read
or write cycle.
SCAPar(2:0) transition and check times are delayed from the rest of the
Secondary Cache interface by one PClock. SCAPar(2:0) transitions occur
one PClock after SCAddr transitions, or when the R4400 is changing from
a read cycle to a write cycle without an address change. SCAPar(2:0)
signals do not follow the timing of SCWr* signals, which are set separately
through the programming of the boot-time mode bits.
The R4400 processor has an internal fault detection latency of 4 PClocks
(clock cycles are described in Chapter 10), whereupon Fault* is
synchronized with the System interface. An output fault detected and
propagated through the R4400 processor internal fault logic in a prior
System interface cycle is reported in the current cycle.
In Complete Master mode, output fault reporting is disabled for the
Secondary Cache interface, but enabled for the following System interface
signals: SysCmd, SysCmdP, SysAD, SysADC, ValidOut*, and Release*.
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