Mips Technologies R4000 - Page 464

Chapter 16
434 MIPS R4000 Microprocessor User's Manual
The signals that are connected in parallel and driven from the System
Interface Master (1 in Figure 16-6) include:
• SysAD(63:0)
• SysCmd(8:0)
• SCAPar(2:0)
Signals that are connected in parallel and driven from the Secondary
Cache Master (2 in Figure 16-6) include:
• SysADC(7:0)
• SysCmdP
• ValidOut*
• Release*
• SCAddr(17:1)
• SCAddr0(W:Z)
• SCOE*
• SCWr(W:Z)*
• SCData(127:0)
• SCDChk(15:0)
• SCTag(24:0)
• SCTChk(6:0)
• SCDCS*
• SCTCS*
It should be noted that the fault detection mechanism associated with the
Fault* pin does not cause any exceptions; the processor continues to run
normally regardless of the state of the Fault* signal. It is up to external
logic to handle an asserted Fault* signal.