MIPS R4000 Microprocessor User's Manual 193
Floating-Point Exceptions
Invalid Operation Exception (V)
The Invalid Operation exception is signaled if one or both of the operands
are invalid for an implemented operation. When the exception occurs
without a trap, the MIPS ISA defines the result as a quiet Not a Number
(NaN). The invalid operations are:
• Addition or subtraction: magnitude subtraction of infinities,
such as: ( + ∞ ) + ( – ∞ ) or ( – ∞ ) – ( – ∞ )
• Multiplication: 0 times ∞, with any signs
• Division: 0/0, or ∞/∞, with any signs
• Comparison of predicates involving < or > without ?, when the
operands are unordered
• Comparison or a Convert From Floating-point Operation on a
signaling NaN.
• Any arithmetic operation on a signaling NaN. A move (MOV)
operation is not considered to be an arithmetic operation, but
absolute value (ABS) and negate (NEG) are considered to be
arithmetic operations and cause this exception if one or both
operands is a signaling NaN.
• Square root: √x, where x is less than zero
Software can simulate the Invalid Operation exception for other
operations that are invalid for the given source operands. Examples of
these operations include IEEE Standard 754-specified functions
implemented in software, such as Remainder: x REM y, where y is 0 or x is
infinite; conversion of a floating-point number to a decimal format whose
value causes an overflow, is infinity, or is NaN; and transcendental
functions, such as ln (–5) or cos–1(3). Refer to Appendix B for examples or
for routines to handle these cases.
Trap Enabled Results: The original operand values are undisturbed.
Trap Disabled Results: A quiet NaN is delivered to the destination
register if no other software trap occurs.
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