Mips Technologies R4000 - Master-Listener Configuration

Chapter 16
432 MIPS R4000 Microprocessor User's Manual
Master-Listener Configuration
As shown in Figure 16-5, the Master-Listener lock step configuration pairs
a Complete Master (mode bits 42 and 18 = 00
2
) with a Complete Listener
(mode bits 42 and 18 = 11
2
). In this configuration, the Complete Listener
has disabled output drivers; otherwise, the two R4400 processors operate
identically, both receiving the same inputs. On all output cycles, the
Complete Listener compares data on the output and I/O buses with
expected data, and asserts the Fault* signal in the event of a
miscomparison.
Figure 16-5 Master-Listener Configuration of Master/Checker Mode
Fault*
External
Agent
R4400
Complete
Master
Secondary cache
Complete Listener
System Interface bus
=?
=?
=?
=?
=?
Secondary cache bus
SCAddr
Maintenance
Processor
Fault*
R4400
SysAD/
SysCmd
SysAD/
SysCmd
SysADC/
SysCmdP
SysAD
/
SysCmd
SysADC/
SysCmdP
SysADC/
SysCmdP
SCAddr
SCData/
SCTag
Data Chk/
Tag Chk
SCData/
SCTag
SCData/
SCTag
Data Chk/
Tag Chk
Data Chk/
Tag Chk