Mips Technologies R4000 - FPU Instruction Pipeline Overview; Instruction Execution

Chapter 6
172 MIPS R4000 Microprocessor User's Manual
6.7 FPU Instruction Pipeline Overview
The FPU provides an instruction pipeline that parallels the CPU
instruction pipeline. It shares the same eight-stage pipeline architecture
with the CPU (see Chapter 3).
Instruction Execution
Figure 6-9 illustrates the 8-instruction overlap in the FPU pipeline.
Figure 6-9 FPU Instruction Pipeline
Figure 6-9 assumes that one instruction is completed every PCycle. Most
FPU instructions, however, require more than one cycle in the EX stage.
This means the FPU must stall the pipeline if an instruction execution
cannot proceed because of register or resource conflicts.
Figure 6-10 illustrates the effect of a three-cycle stall on the FPU pipeline.
(8-Deep)
Current
CPU
Cycle
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
PCycle
MasterClock
Cycle