MIPS R4000 Microprocessor User's Manual 97
Memory Management
TLB Misses
If there is no TLB entry that matches the virtual address, a TLB miss
exception occurs.
†
If the access control bits (D and V) indicate that the
access is not valid, a TLB modification or TLB invalid exception occurs. If
the C bits equal 010
2
, the physical address that is retrieved accesses main
memory, bypassing the cache.
TLB Instructions
Table 4-14 lists the instructions that the CPU provides for working with
the TLB. See Appendix A for a detailed description of these instructions.
Table 4-14 TLB Instructions
† TLB miss exceptions are described in Chapter 5.
Op Code Description of Instruction
TLBP Translation Lookaside Buffer Probe
TLBR Translation Lookaside Buffer Read
TLBWI Translation Lookaside Buffer Write Index
TLBWR Translation Lookaside Buffer Write Random
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