Mips Technologies R4000 - Introduction

Table of Contents
xiv MIPS R4000 Microprocessor User's Manual
1
Introduction
Benefits of RISC Design...........................................................................................2
Shorter Design Cycle...........................................................................................3
Effective Utilization of Chip Area ..................................................................... 3
User (Programmer) Benefits............................................................................... 3
Advanced Semiconductor Technologies..........................................................3
Optimizing Compilers......................................................................................... 4
MIPS RISCompiler Language Suite ..................................................................5
Compatibility............................................................................................................6
Processor General Features.....................................................................................6
R4000 Processor Configurations ............................................................................7
R4400 Processor Enhancements.............................................................................7
R4000 Processor........................................................................................................ 9
64-bit Architecture ............................................................................................... 9
Superpipeline Architecture ................................................................................11
System Interface...................................................................................................11
CPU Register Overview......................................................................................12
CPU Instruction Set Overview...........................................................................14
Data Formats and Addressing...........................................................................24
Coprocessors (CP0-CP2) .....................................................................................27
System Control Coprocessor, CP0.................................................................27
Floating-Point Unit (FPU), CP1 ..................................................................... 30
Memory Management System (MMU).............................................................31
The Translation Lookaside Buffer (TLB)......................................................31
Operating Modes.............................................................................................32
Cache Memory Hierarchy..............................................................................32
Primary Caches................................................................................................ 33
Secondary Cache Interface .............................................................................33