MIPS R4000 Microprocessor User's Manual xv
Table of Contents
2
CPU Instruction Set Summary
CPU Instruction Formats ........................................................................................36
Load and Store Instructions ...............................................................................37
Scheduling a Load Delay Slot........................................................................37
Defining Access Types....................................................................................37
Computational Instructions................................................................................39
64-bit Operations .............................................................................................39
Cycle Timing for Multiply and Divide Instructions................................... 40
Jump and Branch Instructions ...........................................................................41
Overview of Jump Instructions ..................................................................... 41
Overview of Branch Instructions ..................................................................41
Special Instructions..............................................................................................42
Exception Instructions.........................................................................................42
Coprocessor Instructions ....................................................................................42
3
The CPU Pipeline
CPU Pipeline Operation..........................................................................................44
CPU Pipeline Stages................................................................................................. 45
Branch Delay.............................................................................................................48
Load Delay ................................................................................................................48
Interlock and Exception Handling.........................................................................49
Exception Conditions .......................................................................................... 52
Stall Conditions.................................................................................................... 53
Slip Conditions.....................................................................................................53
External Stalls .......................................................................................................53
Interlock and Exception Timing ........................................................................53
Backing Up the Pipeline .................................................................................54
Aborting an Instruction Subsequent to an Interlock.................................. 55
Pipelining the Exception Handling................................................................... 56
Special Cases.........................................................................................................58
Performance Considerations..........................................................................58
Correctness Considerations............................................................................58
R4400 Processor Uncached Store Buffer ............................................................... 59
To Next Page
Loading...