Mips Technologies R4000 - Page 16

Table of Contents
xvi MIPS R4000 Microprocessor User's Manual
4
Memory Management
Translation Lookaside Buffer (TLB) ......................................................................62
Hits and Misses .................................................................................................... 62
Multiple Matches .................................................................................................62
Address Spaces.........................................................................................................63
Virtual Address Space......................................................................................... 63
Physical Address Space.......................................................................................64
Virtual-to-Physical Address Translation..........................................................64
32-bit Mode Address Translation......................................................................65
64-bit Mode Address Translation......................................................................66
Operating Modes .................................................................................................67
User Mode Operations...................................................................................67
Supervisor Mode Operations........................................................................69
Kernel Mode Operations ............................................................................... 73
System Control Coprocessor .................................................................................. 80
Format of a TLB Entry.........................................................................................81
CP0 Registers........................................................................................................84
Index Register (0).............................................................................................85
Random Register (1)........................................................................................ 86
EntryLo0 (2), and EntryLo1 (3) Registers..................................................... 87
PageMask Register (5).....................................................................................87
Wired Register (6)............................................................................................88
EntryHi Register (CP0 Register 10)...............................................................89
Processor Revision Identifier (PRId) Register (15)......................................89
Config Register (16).........................................................................................90
Load Linked Address (LLAddr) Register (17) ............................................ 93
Cache Tag Registers [TagLo (28) and TagHi (29)]......................................93
Virtual-to-Physical Address Translation Process............................................ 95
TLB Misses............................................................................................................97
TLB Instructions...................................................................................................97