MIPS R4000 Microprocessor User's Manual xvii
Table of Contents
5
CPU Exception Processing
How Exception Processing Works......................................................................... 100
Exception Processing Registers..............................................................................101
Context Register (4) .............................................................................................102
Bad Virtual Address Register (BadVAddr) (8)................................................ 103
Count Register (9) ................................................................................................ 103
Compare Register (11)......................................................................................... 104
Status Register (12)...............................................................................................105
Status Register Format....................................................................................105
Status Register Modes and Access States.....................................................109
Status Register Reset .......................................................................................110
Cause Register (13) ..............................................................................................110
Exception Program Counter (EPC) Register (14) ............................................ 112
WatchLo (18) and WatchHi (19) Registers ....................................................... 113
XContext Register (20).........................................................................................114
Error Checking and Correcting (ECC) Register (26)....................................... 115
Cache Error (CacheErr) Register (27)................................................................ 116
Error Exception Program Counter (Error EPC) Register (30)........................ 118
Processor Exceptions ...............................................................................................119
Exception Types...................................................................................................119
Reset Exception Process..................................................................................120
Cache Error Exception Process......................................................................120
Soft Reset and NMI Exception Process.........................................................121
General Exception Process .............................................................................121
Exception Vector Locations................................................................................122
Priority of Exceptions..........................................................................................123
Reset Exception ....................................................................................................124
Soft Reset Exception ............................................................................................125
Address Error Exception.....................................................................................127
TLB Exceptions..................................................................................................... 128
TLB Refill Exception........................................................................................129
TLB Invalid Exception.....................................................................................130
TLB Modified Exception.................................................................................131
Cache Error Exception.........................................................................................132
Virtual Coherency Exception ............................................................................. 133
Bus Error Exception............................................................................................. 134
Integer Overflow Exception ...............................................................................135
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