Mips Technologies R4000 - Double Data Bit ECC Errors

Chapter 16
422 MIPS R4000 Microprocessor User's Manual
Double Data Bit ECC Errors
The following procedure detects double data bit ECC errors.
1. System A transmits:
Data(63:0) = 0x0000 0000 0000 0000
and
ECC(7:0) check code = 0000 0000
2
.
2. System B receives the following incorrect data:
Data(63:0) = 0x0000 0000 0000 0011
and
ECC(7:0) check code = 0000 0000
2
3. System B regenerates the ECC for the received data. The correct
ECC check code for:
Data(63:0) = 0x0000 0000 0000 0011
is
ECC(7:0) = 0011 0000
2
4. A syndrome is generated by the XOR of the System A check bits,
0000 0000
2
, and the System B regenerated check bits, 0011 0000
2
.
The resulting syndrome is 0011 0000
2
.
The syndrome of two 1s (or an even number of 1s) indicates that a
double-bit error has been detected. Double-bit errors cannot be
corrected.