Mips Technologies R4000 - Coherent Write Conflicts

MIPS R4000 Microprocessor User's Manual 281
Cache Organization, Operation, and Coherency
Coherent Write Conflicts
As soon as a write request has been issued to the external agent, the
external agent becomes responsible for the cache line. No conflicts are
possible with a processor write request; however, the external agent must
manage ownership of the cache line while it is waiting to acquire
mastership of the system bus so that it can forward the write request. The
external agent is responsible for the cache line from the time the issue cycle
of the write request completes until the write request is forwarded to the
system bus.
If the response to a coherent read request conflicts with a waiting
processor write request, or with a processor write request that is
transmitting data, the external agent detects the conflict and does not issue
an intervention request to the processor. Instead, it reacts as if an
intervention request has been completed and the line is in the dirty
exclusive state. The external agent indicates takeover and supplies the
read data to the read requester itself without disturbing the processor.
After providing the read data to the read requester, the external agent
must discard the write request if the read request was a read exclusive. In
fact, the external agent can ignore the write request for either type of read,
since processor-supplied read data is also written back to memory.
It is not possible for an invalidate request, or a write request that conflicts
with a waiting processor write request, to appear on the system bus;
before a processor write request can be issued, the state of the processor
cache line must be set to dirty exclusive.