Chapter 10
230 MIPS R4000 Microprocessor User's Manual
SClock
The R4000 processor divides PClock by 2, 3, or 4 (as programmed at boot-
mode initialization) to generate the internal clock signal, SClock. The
R4400 processor divides PClock by 2, 3, 4, 6 or 8 (as programmed at boot-
mode initialization) to generate SClock. The processor uses SClock to
sample data at the system interface and to clock data into the processor
system interface output registers.
The first rising edge of SClock, after ColdReset* is deasserted, is aligned
with the first rising edge of MasterClock.
TClock
TClock (transmit clock) clocks the output registers of an external agent,
†
and can be a global system clock for any other logic in the external agent.
TClock is the same frequency as SClock. When SyncIn is shorted to
SyncOut, the edges of TClock align precisely with the edges of SClock
and MasterClock.
When a delay is added between SyncIn and SyncOut, the TClock at the
pins leads SClock (and thus MasterClock) by the same amount of delay.
If the delay between SyncIn and SyncOut is matched to an external delay
between TClock at the processor and TClock at the external logic, the
TClock at the external logic aligns to SClock and MasterClock.
RClock
The external agent uses RClock (receive clock) to clock its input registers.
The processor generates RClock at the same frequency as TClock, but
RClock always leads TClock and SClock by 25 percent of SClock cycle
time. The relationship between RClock and TClock is independent of the
delay between SyncIn and SyncOut.
PClock-to-SClock Division
Figure 10-3 shows the clocks for a PClock-to-SClock division by 2; Figure
10-4 shows the clocks for a PClock-to-SClock division by 4.
† External agent is defined in Chapter 12.
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