Chapter 12
378 MIPS R4000 Microprocessor User's Manual
Sequential and Subblock Ordering
The order in which data is returned in response to a processor block read
request can be programmed to sequential ordering or subblock ordering,
using the boot-time mode control interface. Appendix C has more
information about subblock ordering. Either sequential or subblock
ordering may be enabled, as follows:
• If sequential ordering is enabled on a block read request, the
processor delivers the address of the doubleword at the start of
the block. An external agent must return the block of data
sequentially from the beginning of the block.
• If subblock ordering is enabled, the processor delivers the
address of the requested doubleword within the block. An
external agent must return the block of data using subblock
ordering, starting with the addressed doubleword.
NOTE: Only R4000SC and R4000MC configurations (using a
secondary cache) can be programmed to use sequential ordering.
For block write requests, the processor always delivers the address of the
doubleword at the beginning of the block; the processor delivers data
beginning with the doubleword at the beginning of the block and
progresses sequentially through the doublewords that form the block.
During data cycles, the valid byte lines depend upon the position of the
data with respect to the aligned doubleword (this may be a byte, halfword,
tribyte, quadbyte/word, quintibyte, sextibyte, septibyte, or an octalbyte/
doubleword). For example, in little-endian mode, on a byte request where
the address modulo 8 is 0, SysAD(7:0) are valid during the data cycles.
12.11 Processor Internal Address Map
External reads and writes provide access to processor internal resources
that may be of interest to an external agent. The processor decodes bits
SysAD(6:4) of the address associated with an external read or write
request to determine which processor internal resource is the target.
However, the processor does not contain any resources that are readable
through an external read request. Therefore, in response to an external
read request the processor returns undefined data and a data identifier
with its Erroneous Data bit, SysCmd(5), set. The Interrupt register is the
only processor internal resource available for write access by an external
request. The Interrupt register is accessed by an external write request
with an address of 000
2
on bits 6:4 of the SysAD bus.
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