Mips Technologies R4000 - 64-Bit Mode Address Translation

Chapter 4
66 MIPS R4000 Microprocessor User's Manual
64-bit Mode Address Translation
Figure 4-3 shows the virtual-to-physical-address translation of a 64-bit
mode address. This figure illustrates the two extremes in the range of
possible page sizes: a 4-Kbyte page (12 bits) and a 16-Mbyte page (24 bits).
• The top portion of Figure 4-3 shows a virtual address with a
12-bit, or 4-Kbyte, page size, labelled Offset. The remaining 28
bits of the address represent the VPN, and index the 256M-
entry page table.
• The bottom portion of Figure 4-3 shows a virtual address with
a 24-bit, or 16-Mbyte, page size, labelled Offset. The remaining
16 bits of the address represent the VPN, and index the 64K-
entry page table.
Figure 4-3 64-bit Mode Virtual Address Translation
11 0
12
63
VPN Offset
6471
ASID
8
Virtual Address with 256M (2
28
) 4-Kbyte pages
23 0
24
24
Offset
Virtual Address with 64K (2
16
)16-Mbyte pages
16 bits = 64K pages
28 bits = 256M pages
12
ASID
VPN
6162 40 39
28
0 or -1
636471 6162 40 24
8
39
16
24
0 or -1
Virtual-to-physical
translation in TLB
Bits 62 and 63 of the virtual
address select user, supervisor,
or kernel address spaces.
Virtual-to-physical
translation in TLB
TLB
35 0
PFN
Offset
TLB
Offset passed
unchanged to
physical
memory
Offset passed
unchanged to
physical
memory
36-bit Physical Address