MIPS R4000 Microprocessor User's Manual 175
Floating-Point Unit
Scheduling FPU Instructions
The floating-point architecture permits the overlapping of floating-point
load, store, and move instructions with some of the other processor
operations.
To permit this, the FPU coprocessor implements three separate operation
(op) units:
• divider
• multiplier
• adder (for remaining operations)
The multiplier and divider can overlap adder operations; however, they
use the adder on their final cycles, which imposes some limitations.
The multiplier can begin a new double-precision multiplication every four
cycles, and a new single-precision multiplication every three cycles. The
adder generally begins a new operation one cycle before the previous
cycle completes; therefore, a floating-point addition or subtraction can
start every three cycles.
The FPU coprocessor pipeline is fully bypassed and interlocked.
FPU Pipeline Overlapping
Each of the three op units is controlled by an FPU resource scheduler,
which issues instructions under constraints described in the following
section. Table 6-15 lists the pipe stages used in each of the op units
(although not all stages are used by each unit).
Table 6-15 FPU Operational Unit Pipe Stages
Stage Description
A FPU Adder Mantissa Add stage
E FPU Adder Exception Test stage
EX CPU EX stage
M FPU Multiplier 1st stage
N FPU Multiplier 2nd stage
R FPU Adder Result Round stage
S FPU Adder Operand Shift stage
U FPU Unpack stage
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