Mips Technologies R4000 - External Write Request Protocol

MIPS R4000 Microprocessor User's Manual 347
System Interface
External Write Request Protocol
External write requests use a protocol identical to the processor single
word write protocol except the ValidIn* signal is asserted instead of
ValidOut*. Figure 12-32 shows a timing diagram of an external write
request, which consists of the following steps:
1. The external agent asserts ExtRqst* to arbitrate for the System
interface.
2. The processor releases the System interface to slave state by asserting
Release*.
3. The external agent drives a write command on the SysCmd bus, a
write address on the SysAD bus, and asserts ValidIn*.
4. The external agent drives a data identifier on the SysCmd bus, data on
the SysAD bus, and asserts ValidIn*.
5. The data identifier associated with the data cycle must contain a
coherent or noncoherent last data cycle indication.
6. After the data cycle is issued, the write request is complete and the
external agent sets the SysCmd and SysAD buses to a tri-state,
allowing the System interface to return to master state. Timings for
the SysADC and SysCmdP buses are the same as those of the SysAD
and SysCmd buses, respectively.
External write requests are only allowed to write a word of data to the
processor. Processor behavior in response to an external write request for
any data element other than a word is undefined.
Figure 12-32 External Write Request, with System Interface initially a Bus Master
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Data0
SysCmd Bus
Write NEOD
ValidOut*
ValidIn*
ExtRqst*
Release*
4
5
6
1
2
3
4
Master
Slave
Master