Mips Technologies R4000 - Page 376

Chapter 12
346 MIPS R4000 Microprocessor User's Manual
Figure 12-30 Secondary Cache Release External Null Request
Figure 12-31 System Interface Release External Null Request
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Unsd
SysCmd Bus
SCNull
ValidOut*
ValidIn*
ExtRqst*
Release*
4
5
1
2
3
Master
Slave
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Unsd
SysCmd Bus
SINull
ValidOut*
ValidIn*
ExtRqst*
Release*
4
5
3
Slave
Master