MIPS R4000 Microprocessor User's Manual 345
System Interface
Any time the processor releases the System interface to slave state to
accept an external request, it also allows the external agent to use the
secondary cache, in anticipation of a cache coherence request. When the
external agent uses the SysAD bus for a transfer unrelated to the processor
(for example, a DMA transfer), this ownership of the secondary cache
prevents the processor from satisfying subsequent primary cache misses.
To satisfy such a primary cache miss, the external agent issues a secondary
cache release external null request, returning ownership of the secondary
cache to the processor.
External null requests require no action from the processor other than to
return the System interface to master state, or to regain ownership of the
secondary cache.
Figures 12-30 and 12-31 show timing diagrams of the two external null
request cycles, which consist of the following steps:
1. The external agent asserts ExtRqst* to arbitrate for the System
interface.
2. The processor releases the System interface to slave state by asserting
Release*.
3. The external agent drives a secondary cache release external null
request command on the SysCmd bus, and asserts ValidIn* for one
cycle to return the secondary cache interface ownership to the
processor.
4. The SysAD bus is unused (does not contain valid data) during the
address cycle associated with an external null request.
5. After the address cycle is issued, the null request is complete.
For a secondary cache release external null request, the System interface
remains in slave state.
For a System interface release external null request, the external agent releases
the SysCmd and SysAD buses, and expects the System interface to return
to master state.
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