Mips Technologies R4000 - Page 232

Chapter 8
202 MIPS R4000 Microprocessor User's Manual
Table 8-1 (cont.) System Interface Signals
†. The SysADC(7:0) bits map to the SysAD bus in this manner: SysADC(7) covers
SysAD(63:56), SysADC(6) covers SysAD(55:48), and so on down to SysADC(0), which
covers SysAD(7:0).
Name Definition Direction Description
SysADC(7:0)
System address/
data check bus
Input/Output
An 8-bit bus containing
check bits for the SysAD
bus.
†
SysCmd(8:0)
System command/
data identifier
Input/Output
A 9-bit bus for command
and data identifier
transmission between the
processor and an external
agent.
SysCmdP
System command/
data identifier bus
parity
Input/Output
A single, even-parity bit for
the SysCmd bus. When the
System interface is set to
parity mode, the processor
also indicates a secondary
cache ECC error by
corrupting the state of the
SysCmdP signal.
ValidIn* Valid input Input
The external agent asserts
ValidIn* when it is driving a
valid address or data on the
SysAD bus and a valid
command or data identifier
on the SysCmd bus.
ValidOut* Valid output Output
The processor asserts
ValidOut* when it is
driving a valid address or
data on the SysAD bus and a
valid command or data
identifier on the SysCmd
bus.
WrRdy* Write ready Input
An external agent asserts
WrRdy* when it can accept
a processor write request.