MIPS R4000 Microprocessor User's Manual 191
Floating-Point Exceptions
The FPU detects the eight exception causes internally. When the FPU
encounters one of these unusual situations, it causes either an IEEE
exception or an Unimplemented Operation exception (E).
Table 7-2 lists the exception-causing situations and contrasts the behavior
of the FPU with the requirements of the IEEE Standard 754.
Table 7-2 FPU Exception-Causing Conditions
† The IEEE Standard 754 specifies an inexact exception on overflow only if the overflow
trap is disabled.
‡ Exponent underflow sets the U and I Cause bits if both the U and I Enable bits are not set
and the FS bit is set; otherwise exponent underflow sets the E Cause bit.
FPA Internal
Result
IEEE
Standard
754
Trap
Enable
Trap
Disable
Notes
Inexact result I I I Loss of accuracy
Exponent overflow O,I
†
O,I O,I Normalized exponent > E
max
Division by zero Z Z Z
Zero is (exponent = E
min
-1,
mantissa = 0)
Overflow on convert V E E Source out of integer range
Signaling NaN
source
VVV
Invalid operation V V V 0/0, etc.
Exponent underflow U E UI
‡
Normalized exponent < E
min
Denormalized or
QNaN
None E E
Denormalized is (exponent =
E
min
-1 and mantissa <> 0)
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