MIPS R4000 Microprocessor User's Manual D-1
Output Buffer ∆i/∆t Control Mechanism
D
The speed of the R4000 output drivers is controlled by a negative feedback
loop that insures the drive-off times are only as fast as necessary to meet
the system requirement for single cycle transfers. This guarantees the
minimum ground bounce from L*(∆i/∆t) of the switching buffers,
consistent with the system timing requirements.
D.1 Mode Bits
Four bits are used to control the pull-up and pull-down delays. These bits
are initially set to the values in the mode bits InitN(3:0) for pull-up and
InitP(3:0) for pull-down. If the ∆i/∆t control mechanism is enabled, it is
recommended to load the mode bits InitP(3:0) and InitN(3:0) to the values
which provide the slowest slew rate.
Under normal conditions, the ∆i/∆t control mechanism is enabled to
compensate the output buffer delay for any changes in the temperature or
power supply voltage. The EnblDPLL mode bit is set for this mode of
operation.
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