Mips Technologies R4000 - Page 718

Appendix C
C-6 MIPS R4000 Microprocessor User's Manual
Table C-3 Sequence of Doublewords Transferred Using Subblock Ordering: Address 0101
2
Cycle
Starting Block
Address
Binary Count
Double Word
Retrieved
1 0101 0000 0101
2 0101 0001 0100
3 0101 0010 0111
4 0101 0011 0110
5 0101 0100 0001
6 0101 0101 0000
7 0101 0110 0011
8 0101 0111 0010
9 0101 1000 1101
10 0101 1001 1100
11 0101 1010 1111
12 0101 1011 1110
13 0101 1100 1001
14 0101 1101 1000
15 0101 1110 1011
16 0101 1111 1010