MIPS R4000 Microprocessor User's Manual A-147
CPU Instruction Set Details
Format:
SRAV rd, rt, rs
Description:
The contents of general register rt are shifted right by the number of bits
specified by the low-order five bits of general register rs, sign-extending
the high-order bits.
The result is placed in register rd.
In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.
Operation:
Exceptions:
None
SRAV
g
31 2526 2021 1516
SPECIAL rs rt
655
rd 0 SRAV
55 6
11 10 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
SRAV
Arithmetic Variable
32 T: s ← GPR[rs]
4...0
GPR[rd] ← (GPR[rt]
31
)
s
|| GPR[rt]
31...s
64 T: s ← GPR[rs]
4...0
temp ← (GPR[rt]
31
)
s
|| GPR[rt]
31...s
GPR[rd] ← (temp
31
)
32
|| temp
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