Appendix A
A-148 MIPS R4000 Microprocessor User's Manual
Format:
SRL rd, rt, sa
Description:
The contents of general register rt are shifted right by sa bits, inserting
zeros into the high-order bits.
The result is placed in register rd.
In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.
Operation:
Exceptions:
None
SRL
Shift Right Logical
31 2526 2021 1516
SPECIAL rt
655
rd sa SRL
55 6
11 10 6 5 0
0 0 0 0 0 0 0 0 0 0 1 0
SRL
0
0 0 0 0 0
32 T: GPR[rd] ← 0
sa
|| GPR[rt]
31...sa
64 T: s ← 0 || sa
temp ← 0
s
|| GPR[rt]
31...s
GPR[rd] ← (temp
31
)
32
|| temp
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