MIPS R4000 Microprocessor User's Manual 117
CPU Exception Processing
Table 5-10 (cont.) CacheErr Register Fields
Field Description
ES
Indicates the error occurred while accessing primary or secondary cache in
response to an external request.
0 → internal reference
1 → external reference
EE This bit is set if the error occurred on the SysAD bus.
EB
This bit is set if a data error occurred in addition to the instruction error
(indicated by the remainder of the bits). If so, this requires flushing the
data cache after fixing the instruction error.
EI
This bit is set on a secondary data cache ECC error while refilling the
primary cache on a store miss. The ECC handler must first do an Index
Store Tag to invalidate the incorrect data from the primary data cache.
EW
This bit is only available on the R4400 processor. It is set on an
multiprocessor cache error when the CacheErr register is already holding
the values of a previous cache error. This bit could be set by the processor
from the time the CacheErr register is loaded due to an error until the time
that an ERET instruction is executed. Once the EW bit is set, it can only be
cleared by a reset. The following errors set the EW bit:
• Secondary cache tag errors arising from an external request
(multibit errors only)
• Secondary cache data errors arising from an external update
• Primary cache tag errors arising from an external request
SIdx
Bits pAddr(21:3) of the reference that encountered the error (which is not
necessarily the same as the address of the doubleword in error, but is
sufficient to locate that doubleword in the secondary cache).
PIdx
Bits vAddr(14:12) of the doubleword in error (used with SIdx to construct
a virtual index for the primary caches).
0 Reserved. Must be written as zeroes, and returns zeroes when read.
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