MIPS R4000 Microprocessor User's Manual 111
CPU Exception Processing
Figure 5-7 Cause Register Format
Table 5-6 Cause Register ExcCode Field
Exception
Mnemonic Description
Code Value
0 Int Interrupt
1 Mod TLB modification exception
2 TLBL TLB exception (load or instruction fetch)
3 TLBS TLB exception (store)
4 AdEL Address error exception (load or instruction fetch)
5 AdES Address error exception (store)
6 IBE Bus error exception (instruction fetch)
7 DBE Bus error exception (data reference: load or store)
8 Sys Syscall exception
9 Bp Breakpoint exception
10 RI Reserved instruction exception
11 CpU Coprocessor Unusable exception
12 Ov Arithmetic Overflow exception
13 Tr Trap exception
14 VCEI Virtual Coherency Exception instruction
15 FPE Floating-Point exception
16–22 – Reserved
23 WATCH Reference to WatchHi/WatchLo address
24–30 – Reserved
31 VCED Virtual Coherency Exception data
Cause Register
1
IP7
31 1527 16
212
876 2 0
81251
0
Exc
Code
1
0
0
282930
BD
0
CE
IP0
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