Mips Technologies R4000 - Page 40

Chapter 1
10 MIPS R4000 Microprocessor User's Manual
Figure 1-1 R4000 Processor Internal Block Diagram
System
Control
S-cache
Control
Data Cache P-cache
Control
Instruction
Cache
Exception/Control
Memory Management
Translation
CPU Registers
ALU
Load Aligner/Store Driver
Integer Multiplier/Divider
Address Unit
PC Incrementer
FPU Registers
Pipeline Bypass
FP Multiplier
FP Divider
FP Add, Convert
Registers
Registers
Lookaside
Buffers
Square Root
CP0
CPU
FPU
Pipeline Control
64-bit System Bus