MIPS R4000 Microprocessor User's Manual 261
Cache Organization, Operation, and Coherency
Figure 11-9 Primary Data Cache State Diagram
If the system is in no-secondary-cache mode, the cache state provided by
the system is ignored, and the primary data cache state is set to dirty
exclusive.
Write hit
Read hit
Write hit [update]
Read hit
Update received
Clean
Exclusive
Dirty
Exclusive
Invalid
Shared
I/O invalidate received
I/O invalidate received
Read hit
Write hit
Write hit [sharable]
Bus read [intervention]
Bus read
Invalidate received
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