Mips Technologies R4000 - Page 292

Chapter 11
262 MIPS R4000 Microprocessor User's Manual
Figure 11-10 Secondary Cache State Diagram
Bus read [intervention]
Read hit
Read hit,
Write hit
Bus read [intervention]
Write hit [update],
Read hit
Read hit,
Update received
Invalidate
received
I/O
invalidate
received
Invalid
Write hit
Update
received
Write hit
[invalidate]
Bus
read
I/O
invalidate
received
Invalidate
received
Write hit
[update]
Dirty
Shared
Shared
Dirty
Exclusive
Clean
Exclusive
Write hit [invalidate]