MIPS R4000 Microprocessor User's Manual 263
Cache Organization, Operation, and Coherency
The state of a secondary cache line is provided by the external agent and
is set as follows:
Case 1. If the cache line is not present in another cache, it should be loaded
in the clean exclusive state.
Case 2. If the cache line is retained by another cache and the state of the
line in that cache remains shared or dirty shared, the line should
be loaded in the shared state.
Case 3. If the cache line is retained by another cache and the cache
relinquishes ownership to the processor making the read request,
the line should be returned in the dirty shared state.
Case 4. If the cache line is retained by another cache and ownership is
relinquished to memory, the line should be loaded in the shared
state.
Case 5. If the cache line is relinquished by another cache and ownership
is transferred to the processor making the read request, the line
should be loaded in the dirty exclusive or dirty shared state.
For case 1, if the refill occurs on a store miss, the processor changes the
cache line state to dirty exclusive. For each of the remaining cases listed
above, the R4000 processor passes the state received from the external
agent to the secondary cache.
The invalid state is never used for a refill. Software, however, should
initialize the secondary cache to the invalid state after the system is
powered up.
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