Chapter 11
284 MIPS R4000 Microprocessor User's Manual
Figure 11-14 Cache Load Miss Cycle: External Intervention
4. As shown in Figure 11-14, external agent E
A
reads the CRR from the
bus.
5. To service this CRR, E
A
issues an external intervention request (EIR)
to processor A, P
A
.
6. P
A
receives the EIR and examines its secondary cache, S
A
.
7. Depending on the type of intervention request—based on the state of
the SysCmd(3) bit—one of the following actions is taken:
• If the cache line in S
A
is in the dirty exclusive state, the entire
cache line is returned.
• Otherwise, P
A
just returns the state of the secondary cache line.
In Figure 11-14 the retrieved data is in the dirty exclusive state (DE),
servicing a load miss, when the state of cache line S
A
goes from dirty
exclusive to dirty shared (DS),
†
indicating P
A
is owner of the line.
† Assuming DS mode is enabled.
DE
Secondary
Cache A (S
A
)
System Bus
Secondary
Cache B (S
B
)
2
3
1
4
5
6
Processor
A (P
A
)
External
Agent A (E
A
)
Processor
B (P
B
)
External
Agent B (E
B
)
External
Intervention
Request (EIR)
7
Memory
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