Mips Technologies R4000 - Page 315

MIPS R4000 Microprocessor User's Manual 285
Cache Organization, Operation, and Coherency
Figure 11-15 Cache Load Miss Cycle: Read Response
8. Figure 11-15 shows the cache state and cache data returned from P
A
,
through E
A
to the bus.
9. This cache state and data are returned to E
B
.
10. E
B
issues a read response to P
B.
11. P
A
remains owner of the cache line.
DS
Secondary
Cache A (S
A
)
Processor
A (P
A
)
External
Agent A (E
A
)
Processor
B (P
B
)
External
Agent B (E
B
)
System Bus
Secondary
Cache B (S
B
)
2
3
1
4
7
8
9
10
5
6
Read
Response
S
11
Memory