Mips Technologies R4000 - Page 457

MIPS R4000 Microprocessor User's Manual 427
Error Checking and Correcting
Table 16-2 Error Checking and Correcting Summary for Internal Transactions
† Read-Modify-Write cycle
‡ If error level (ERL bit of the Status register) is 1, the error is reported to the Fault* pin.
* Only if the current CACHE op needs to modify and write back the tag.
Bus
Store to
Shared
Cache Line
Cache
Instruction
Secondary
Cache Load
from System
Interface
Secondary
Cache Write
to System Interface
Processor or
Secondary Cache
Data
NA
Check on
cache
writeback;
Trap on Error
From
System
Interface
unchanged
Checked; Trap on
Error
Secondary Cache
Data Check Bits
NA
Check on
cache
writeback;
Trap on Error
From
System
Interface
unchanged
Checked; Trap on
Error
Secondary Cache Tag
and Check Bits
Checked on
read part of
RMW
†
; correct
Secondary
cache tag; Trap
on Error
Checked;
corrected
Secondary
cache tag*;
Trap on Error
Generated
Checked; not
corrected; Trap on
Error
System Interface
Address, Command,
and Check Bits:
Transmit
Generated Generated Generated Generated
System Interface
Address, Command,
and Check Bits:
Receive
NA NA
Not
Checked
NA
System Interface Data
From
Processor
From Primary
or Secondary
Cache
Checked;
Trap on
Error
‡
From Secondary
Cache
System Interface Data
Check Bits
Generated
From Primary
or Secondary
Cache
Checked;
Trap on
Error
‡
From Secondary
Cache (SysCmdP
signal corrupted
if System
interface set to
parity mode)