Mips Technologies R4000 - Page 458

Chapter 16
428 MIPS R4000 Microprocessor User's Manual
Table 16-3 Error Checking and Correcting Summary for External Transactions
† Read-Modify-Write cycle
‡ Only the pair of doublewords accessed on the read portion of RMW is checked.
Bus
Read
Request
Write
Request
Invalidate
Request
Update
Request
Processor or
Secondary Cache
Data
NA NA Not Checked
Checked on read
part of RMW
†
;
Trap on Error
‡
Secondary Cache
Data Check Bits
NA NA Not Checked
Checked on read
part of RMW
†
;
Trap on Error
‡
;
Generation on
write part of
RMW if written
Secondary Cache Tag
and Check Bits
NA NA
Checked on
read part of
RMW
†
; Trap
on Error
‡
;
Generation
on write part
of RMW if
written
Checked on read
part of RMW
†
;
Trap on Error;
Generation on
write part of
RMW if written
System Interface
Address, Command
and Check Bits:
Transmit
Generated NA NA NA
System Interface
Address, Command
and Check Bits:
Receive
Not
Checked;
reported to
the Fault*
pin
Not
Checked;
reported to
the Fault*
pin
Not Checked;
reported to
the Fault* pin
Not Checked;
reported to the
Fault* pin
System Interface Data
From
Processor
Checked;
Trap on
Error
Not Checked
Not Checked;
reported to the
Fault* pin
System Interface Data
Check Bits
Generated
Checked;
Trap on
Error
Not Checked
Not Checked;
reported to the
Fault* pin