Mips Technologies R4000 - Page 459

MIPS R4000 Microprocessor User's Manual 429
Error Checking and Correcting
Table 16-4 Error Checking and Correcting Summary for External Transactions
† Read-Modify-Write cycle
Bus
Intervention Request
Data Returned
Intervention Request
State Returned
Snoop Request
Processor or
Secondary Cache
Data
Checked; Trap on
Error
Not Checked Not Checked
Secondary Cache
Data Check Bits
Checked; Trap on
Error
Not Checked Not Checked
Secondary Cache Tag
and Check Bits
Checked and
corrected on read
part of RMW
†
; Trap
on Error;
Generation on write
part of RMW if
written.
Checked and
corrected on read part
of RMW
†
; Trap on
Error; Generation on
write part of RMW if
written.
Checked and
corrected on
read part of
RMW
†
;
Trap on Error;
Generation on
write part of
RMW if
written.
System Interface
Address, Command,
and Check Bits:
Transmit
Generated Generated Generated
System Interface
Address, Command,
and Check Bits:
Receive
Not Checked;
reported to the
Fault* pin
Not Checked;
reported to the Fault*
pin
Not Checked;
reported to the
Fault* pin
System Interface Data
From Secondary
Cache
NA NA
System Interface Data
Check Bits
From Secondary
Cache
NA NA