Chapter 16
410 MIPS R4000 Microprocessor User's Manual
Secondary Cache Data Bus SECDED Code
The SECDED code protecting secondary cache data bus has the properties
listed below:
• It corrects single-bit errors.
• It detects double-bit errors.
• It detects 3- or 4-bit errors within a nibble
†
.
• It provides 64 data bits protected by 8 check bits, and yields 8-
bit syndromes (the syndrome is a generated value used to detect
an error, and locate the position of the single bit in error).
• It is a minimal-length code; each parity tree used to generate
the 8-bit syndrome has only 27 inputs, the minimum number
possible.
• It provides byte Exclusive-ORs (XORs) of the data bits as part
of the XOR trees used to build the parity generators. This
allows selection of byte parity out of the XOR trees that
generate or check the code.
• Single-bit errors are indicated either by syndromes that contain
exactly three 1s, or by syndromes that contain exactly five 1s
(in which bits 0-3 or bits 4-7 of the syndrome are all 1s).
‡
• Double-bit errors are indicated by syndromes that contain an
even number of 1s.
• 3-bit errors within a nibble are indicated by syndromes that
contain five 1s, in which bits 0-3 of the syndrome and bits 4-7
of the syndrome are not all 1s.
• 4-bit errors within a nibble are indicated by syndromes that
contain four 1s. Because this is an even number of 1s, 4-bit
errors within a nibble look like double-bit errors.
† A nibble is defined here as any group of four bits located within the vertical rules of Figure
16-1.
‡ This makes it possible to decode the syndrome to find which data bit is in error, using 4-
input NAND gates, provided a pre-decode AND of bits 0-3 and bits 4-7 of the syndrome
is available. For the check bits, a full 8-bit decode of the syndrome is required.
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