MIPS R4000 Microprocessor User's Manual 411
Error Checking and Correcting
Secondary Cache Tag Bus SECDED Code
The SECDED ECC code protecting the secondary cache tag bus has the
following properties:
• It corrects single-bit errors.
• It detects double-bit errors.
• It detects 3- or 4-bit errors within a nibble.
• It provides 25 data bits protected by 7 check bits, yielding 7-bit
syndromes.
• It provides byte XORs of the data bits as part of the XOR trees
used to build the parity generators. This allows selection of
byte parity out of the XOR trees that generate or check the
code.
• Single-bit errors are indicated by syndromes that contain
exactly three 1s. This makes it possible to decode the
syndrome to find which data bit is in error with 3-input NAND
gates. For the check bits, a full 7-bit decode of the syndrome is
required.
• Double-bit errors are indicated by syndromes that contain an
even number of 1s.
• 3-bit errors within a nibble are indicated by syndromes that
contain either five 1s or seven 1s.
• 4-bit errors within a nibble are indicated by syndromes that
contain either four 1s or six 1s. Because these are even
numbers of 1s, 4-bit errors within a nibble look like double-bit
errors.
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