MIPS R4000 Microprocessor User's Manual 83
Memory Management
Figure 4-10 Fields of the EntryLo0 and EntryLo1 Registers
G
D
24
31
PFN
31
0
30 29
2
3111
24
PFN
30 29
2
CVD
311
12356
G
1
0
0
PFN
......Page frame number; the upper bits of the physical address.
C
..........Specifies the TLB page coherency attribute; see Table 4-6.
D
..........Dirty. If this bit is set, the page is marked as dirty and, therefore, writable. This bit is
actually a write-protect bit that software can use to prevent alteration of data.
V
..........Valid. If this bit is set, it indicates that the TLB entry is valid; otherwise, a TLBL or TLBS
miss occurs.
G
..........Global. If this bit is set in both Lo0 and Lo1, then the processor ignores the ASID during
TLB lookup.
0
...........Reserved. Must be written as zeroes, and returns zeroes when read.
24
63
PFN
63
0
34
CVD
3111
24
PFN
30 29
34
CV
311
12356
G
1
0
0
EntryLo0 and EntryLo1 Registers
30 29 012356
GCVD
012
3
56
32-bit
Mode
32-bit
Mode
64-bit
Mode
64-bit
Mode
To Next Page
Loading...