Chapter 4
82 MIPS R4000 Microprocessor User's Manual
The format of the EntryHi, EntryLo0, EntryLo1, and PageMask registers are
nearly the same as the TLB entry. The one exception is the Global field
(G bit), which is used in the TLB, but is reserved in the EntryHi register.
Figures 4-9 and 4-10 describe the TLB entry fields shown in Figure 4-8.
Figure 4-9 Fields of the PageMask and EntryHi Registers
12
31
13
0
MASK
31
VPN2
19
0
5
8
ASID
1213
7
25 24 13 12
87
PageMask Register
EntryHi Register
00
0
VPN2
... Virtual page number divided by two (maps to two pages).
ASID
.... Address space ID field. An 8-bit field that lets multiple processes share the TLB;
each process has a distinct mapping of otherwise identical virtual page numbers.
R
.......... Region. (00 → user, 01 → supervisor, 11 → kernel) used to match vAddr
63...62
Fill
........ Reserved. 0 on read; ignored on write.
0
........... Reserved. Must be written as zeroes, and returns zeroes when read.
63
VPN2
27
0
5
8
ASID
1213 87
0
2
62 61 40 39
22
FILLR
32-bit
Mode
32-bit
Mode
64-bit
Mode
Mask
.....Page comparison mask.
0
...........Reserved. Must be written as zeroes, and returns zeroes when read.
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