Chapter 12
334 MIPS R4000 Microprocessor User's Manual
Processor block write requests are issued with the System interface in
master state, as described below; a processor coherent block request for
eight words of data is illustrated in Figures 12-20 and 12-21.
1. The processor issues a write command on theSysCmd bus and a write
address on the SysAD bus.
2. The processor asserts ValidOut*.
3. The processor drives a data identifier on the SysCmd bus and data on
the SysAD bus.
4. The processor asserts ValidOut* for a number of cycles sufficient to
transmit the block of data.
5. The data identifier associated with the last data cycle must contain a
last data cycle indication.
NOTE: As shown in Figure 12-21, however, the first data cycle does
not have to immediately follow the address cycle.
Figures 12-20 and 12-21 illustrate a processor coherent block request for
eight words of data.
Figure 12-20 Processor Coherent Block Write Request Protocol
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Data0 Data1 Data2 Data3
SysCmd Bus
Write CData CData CData CEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
5
2
4
1
Master
3
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