MIPS R4000 Microprocessor User's Manual 57
The CPU Pipeline
The decision whether or not to advance the pipeline is derived from these
three rules:
• All possible fault-causing events, such as cache misses,
translation exceptions, load interlocks, etc., must be
individually evaluated.
• The fault to be serviced is selected, based on a predefined
priority as determined by the pipeline stage of the asserted
faults.
• Pipeline advance control signals are buffered and distributed.
Figure 3-10 illustrates this process.
Figure 3-10 Pipeline Advance Decision
Clock
Phase
Cycle
12
Run Run Run Run
12 1212
Evaluate Resolve Buffer
Evaluate Resolve Buffer
Evaluate Resolve Buffer
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