Mips Technologies R4000 - Page 352

Chapter 12
322 MIPS R4000 Microprocessor User's Manual
Table 12-4 Store Miss to Primary and Secondary Caches
Page Attribute
(Write-back
Policy)
Processor
Configuration
State of Data Cache Line Being Replaced
No-Secondary-
Cache Mode
Secondary-Cache Mode
Clean/
Invalid
Dirty
Clean/
Invalid
Dirty
Noncoherent
All R4000
models
NCR
NCR/
W
NCR NCR-W
Exclusive
(write
invalidate)
R4000SC
R4000MC
N/A N/A R
Ex
R
Ex
-W
Shareable
(write
invalidate)
R4000MC N/A N/A R
Ex
R
Ex
-W
Update
(write update)
R4000MC N/A N/A
Dis
(1)
R/U
En
(2)
R-PU
Dis
(1)
R-W/U
En
(2)
R-PU-W
NCR...................Processor noncoherent block read request
NCR/W.............Processor noncoherent block read request followed by processor block
write request
NCR-W..............Cluster: Processor noncoherent block read request with write forthcoming
followed by processor block write request
R
Ex
......................Processor coherent block read request with exclusivity
R
Ex
-W ................Cluster: Processor coherent block read request with exclusivity and write
forthcoming followed by processor block write request
R/U....................Processor coherent block read request followed by processor update
request (if read response data is shared or dirty shared)
R-PU ..................Cluster: Processor coherent block read request followed by processor
potential update request
R-PU-W.............Cluster: Processor coherent block read request followed by processor
potential update request, followed by processor block write request
R-W/U ..............Cluster: Processor coherent block read request with write forthcoming
followed by processor block write request, followed by processor update
request (if read response data is shared or dirty shared)
Dis
(1)
..................Potential update disable [Modebit(20): PotUpdDis = 1]
En
(2)
...................Potential update enable [Modebit(20): PotUpdDis = 0]