Mips Technologies R4000 - Preface; Overview of the Contents

MIPS R4000 Microprocessor User's Manual vii
Preface
This book describes the MIPS R4000 and R4400 family of RISC
microprocessors (also referred to in this book as processor).
Overview of the Contents
Chapter 1 is a discussion (including the historical context) of RISC
development in general, and the R4000 microprocessor in particular.
Chapter 2 is an overview of the CPU instruction set.
Chapter 3 describes the operation of the R4000 instruction execution
pipeline, including the basic operation of the pipeline and
interruptions that are caused by interlocks and exceptions.
Chapter 4 describes the memory management system including
address mapping and address spaces, virtual memory, the translation
lookaside buffer (TLB), and the System Control Processor (CP0).
Chapter 5 describes the exception processing resources of R4000
processor. It includes an overview of the CPU exception handling
process and describes the format and use of each CPU exception
handling register.