Preface
viii MIPS R4000 Microprocessor User's Manual
Chapter 6 describes the Floating-Point Unit (FPU), a coprocessor for
the CPU that extends the CPU instruction set to perform floating-
point arithmetic operations. This chapter lists the FPU registers and
instructions.
Chapter 7 describes the FPU exception processing.
Chapter 8 describes the signals that pass between the R4000 processor
and other components in a system. The signals discussed include the
System interface, the Clock/Control interface, the Secondary Cache
interface, the Interrupt interface, the Initialization interface, and the
JTAG interface.
Chapter 9 describes in more detail the Initialization interface, which
includes the boot modes for the processor, as well as system resets.
Chapter 10 describes the clocks used in the R4000 processor, as well as
the processor status reporting mechanism.
Chapter 11 discusses cache memory, including the operation of the
primary and secondary caches, and cache coherency in a
multiprocessor system.
Chapter 12 describes the System interface, which allows the processor
access to external resources such as memory and input/output (I/O).
It also allows an external agent access to the internal resources of the
processor, such as the secondary cache.
Chapter 13 describes the Secondary Cache interface, including read
and write cycle timing. This chapter also discusses the interface buses
and signals.
Chapter 14 describes the Joint Test Action Group (JTAG) interface.
The JTAG boundary scan mechanism tests the interconnections
between the R4000 processor, the printed circuit board to which it is
mounted, and other components on the board.
Chapter 15 describes the single nonmaskable processor interrupt,
along with the six hardware and two software processor interrupts.
Chapter 16 describes the error checking and correcting (ECC)
mechanisms of the R4000 processor.
To Next Page
Loading...