MIPS R4000 Microprocessor User's Manual ix
Preface
Appendix A describes the R4000 CPU instructions, in both 32- and 64-
bit modes. The instruction list is given in alphabetical order.
Appendix B describes the R4000 FPU instructions, listed
alphabetically.
Appendix C describes sub-block ordering, a nonsequential method of
retrieving data.
Appendix D describes the output buffer and the ∆i/∆t control
mechanism.
Appendix E describes the passive components that make up the
phase-locked loop (PLL).
Appendix F describes Coprocessor 0 hazards.
Appendix G describes the R4000 pinout.
A Note on Style
A brief note on some of the stylistic conventions used in this book: bits,
fields, and registers of interest from a software perspective are
italicized (such as Config register); signal names of more importance
from a hardware point of view are rendered in bold (such as Reset*).
A range of bits uses a colon as a separator; for instance, (15:0)
represents the 16-bit range that runs from bit 0, inclusive, through bit
15. (In some places an ellipsis may used in place of the colon for
visibility: (15...0).)
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